The present invention relates generally to semiconductor memory device programming, and more particularly to the formation and implementation of high current interconnect structures for integrated circuit (IC) memory device programming.
Programmable semiconductor devices such as dynamic random access memory (DRAM), flash memory, and particularly magnetic random access memory (MRAM), typically require large current pulses to properly program these devices. Wide interconnect lines are required to carry large currents for programming these memory devices. Previously, the large width lines did not present an issue with the semiconductor geometries. However, today's increasingly smaller geometries entering into the sub-micron region are forcing designers to investigate every aspect of the IC design to achieve these smaller and smaller geometries. This investigation also includes the wide interconnect high current lines within an IC that are used for IC memory device programming. These wide interconnect lines are inhibiting the memory cell size reduction needed for smaller geometries. Thus, narrower (minimum) feature size interconnect lines must be incorporated into today's IC designs for memory programming without adversely affecting circuit reliability.
Although reducing the width of the high current programming lines in memory devices appears to be an easy solution, in reality the reduction of the interconnect line width beyond a point for a given current results in a phenomenon called “electro-migration”, which adversely impacts the line reliability.
Electro-migration (EM) is the mass transport of a metal due to the momentum transfer between conducting electrons and diffusing metal atoms. A less complex definition of electro-migration is the drift of atoms under the influence of strong electron winds. Within ICs, current densities in metal lines, especially the high current programming lines, can attain huge values (MA/cm2). The conventional method to obtain reliable circuits and avoid the high current densities is to provide sufficiently wide metal lines. However, the continual reduction of circuit geometries as presented above, eliminates this as a viable solution. The most common failure modes in metallic interconnections are related to EM. Early effects in electro-migration are resistance change and the evolution of mechanical stress in grains and regions of grain boundaries (cluster regions). The large stress gradients induce a piezo-resistive effect that in turn changes the line resistance. Two-dimensional simulations have shown that the critical length of a grain in which a mechanical stress gradient and diffusion force can still be built up will balance the electron wind force. This grain length, which negates the EM influence, is commonly known by those skilled in the art as the “Blech length” or “Short length”. “Short length” lines (or grains) shorter than this length are considered “electro-migration hard”. The “Short length” line length where EM effects are eliminated is typically less than 10 um for IC circuit structures. Electro-migration causes failures in microelectronic components by creating voids, which eventually cause open circuits and hillocks, thereby causing short circuits, depending upon the metallization geometry as well as the proximity of one metal line to another.
In state of the art metallization systems, EM becomes noticeable when current densities approach approximately 106 A/cm2. However, EM failures have been observed at much lower current densities, which indicate serious reliability problems. As semiconductor device features are reduced further, current densities increase with the metallization layer complexity. Therefore, it is essential to reduce/eliminate the EM induced failure mode in today's sub-micron designs to attain the maximum circuit reliability. The high current programming lines of semiconductor memory devices are particularly vulnerable to EM effects.
Therefore, desirable in the art of IC memory device programming are improved high current interconnect structures that eliminate the electro-migration effects due to the high current densities for these IC memory devices.